1. Field of the Invention
The present invention relates to the field of liquid crystal display, and in particular to designing and manufacturing methods of TFT LCD (Thin-Film Transistor Liquid Crystal Display) array positioning mark.
2. The Related Arts
A TFT (Thin-Film Transistor) LCD is a thin-film field-effect transistor LCD, which is one of active matrix liquid crystal displays (AM-LCDs). A liquid crystal display, particularly a TFT-LCD, is the only display device that completely matches and gets beyond CRT (Cathode Ray Tube) displays for general performances, including brightness, contrast, power consumption, lifespan, volume, and weight and shows excellent performances, good mass productivity, high automatization, low raw material cost, and wide space of development, and will be soon a main-stream product of new eras and a sparking spot of worldwide economic growth of the 21st century. The liquid crystal displays are mostly backlighting liquid crystal displays that are generally composed of a liquid crystal display panel and a backlight module. A general liquid crystal display panel comprises a color filter (CF) substrate and a thin-film transistor (TFT) array substrate. The CF substrate comprises a plurality of color filters and a common electrode. The TFT array substrate comprises a plurality of parallel scan lines, a plurality of parallel data lines, a plurality of thin-film transistors, and a pixel electrode.
An essential manufacturing process of a typical LCD module comprises three processes, namely an array process, a cell process, and a module process. Among these processes, the array process generally involves techniques of film coating, exposure, development, and etching for forming TFTs on a glass substrate; the cell process generally involves cutting and breaking of liquid crystal and filling of liquid crystal; and the module process generally involves adding driving chips, printed wiring boards, and backlight modules to the cutting-completed panels.
In the field of semiconductor technology, photolithography is one of the indispensable steps of the manufacturing process. As is well known in the industry, the photolithographic process generally involves the following steps: coating a photoresist on a substrate and subjecting the photoresist to exposure with a mask in order to define a circuit pattern corresponding to an electronic product in order to subject the substrate under the photoresist to a subsequent etching process to form the desired circuit pattern. Certainly, completion of the manufacture of an electronic product requires several times of repeating the above steps. Taking the TFT LCD as an example for illustration, multiple rounds of masking operation must be applied to carry out photolithography in order to form a stacked structure. For the common designs of TFT LCD array, five masking operations are used to carry out photolithography for respectively forming circuit patterns of five different layers including a gate electrode (GE) layer, a semiconductor (SE) layer, a source drain (SD) layer, a contact hole (CH) layer, a pixel electrode (PE) layer.
As is well known in the industry, before the exposure process is carried out, the masks must be accurately aligned with the substrate in order to have the circuit pattern accurately projected onto the substrate. A positioning mark is generally used to achieve the alignment between the masks and the substrate. Generally, the mask associated with the gate electrode layer (the first layer) contains, in addition to a circuit pattern associated with the electronic product, a positioning mark that has been defined in advance, so that in performing the exposure operation of the gate electrode layer, the positioning mark will be simultaneously formed on the substrate through the mask of the gate electrode layer. The multiple subsequent masks (such as the masks corresponding to the semiconductor layer, the source drain layer, the contact hole layer, and the pixel electrode layer) are also provided with pre-defined positioning marks, so that before the exposure operations of the semiconductor layer, the source drain layer, the contact hole layer, and the pixel electrode layers are carried out, the positioning marks provided on the masks are used to align with the positioning mark that was previously formed on the substrate in order to ensure the accuracy of exposure operations.
The positioning marks used in the known techniques are mostly completed with gate electrode metal of the first layer. However, the first layer metal positioning mark will then be subjected to the high temperature array and cell processes so that the pattern of the metal positioning mark may readily undergo deformation and shifting and consequently, positioning failure may readily occur in the cell and module processes. Taking the conventional TFT LCD array design that adopts five rounds of masking operation as an example, a positioning mark is generally designed on a periphery of an array substrate for subsequent use with the array and cell processes. Most of the positioning marks are formed with the gate or SD metal (but most positioning marks are still formed by using the gate metal of the first layer). On the other hand, there is generally a gate insulation layer formed on the gate electrode layer; an etch stop (ES) layer serving as a protection layer is generally formed on the semiconductor layer; a passivation (PV) layer serving as a protection layer is generally formed on the SD layer, these gate insulation layer, etch stop layer, and passivation layer being generally formed of silicon nitrides. For the conventional TFT LCD array design that adopts five rounds of masking operation, a second layer of silicon nitride layer and a fourth layer of silicon nitride protection layer are formed on the metal-made positioning marks and during the film formations of the second and fourth silicon nitride layers, the metal-made positioning mark is readily susceptible to the influences caused by the high temperature of the formation of the films and the stresses of the silicon nitride films, resulting in deformation of the positioning mark that may lead to positioning failure in the subsequent processes. The machines of the array process have improved accuracy and the extent of deformation of the positioning mark is less significant when passing through only the array process. However, once additionally subjected to the high temperature cell process, together with the fact that the machines of the cell process are generally of less accuracy than those of the array process, the metal positioning mark commonly undergoes deformation, shifting, and incorrect positioning of the metal positioning mark during the cell and module processes. Thus, further improvement is necessary.